Overview
Computer Architecture: Pipeline and Parallel Processor Design was designed for a graduate level course on computer architecture and organization. The book's content, especially the last half of the book, represents the most advanced material that a typical graduate student studies before directly encountering the design process. The text avoids extensive compendiums of current features of various processors or technologies, just as it stresses concepts that underlie these processor designs. It abstracts the essential elements of processor design and emphasizes a design methodology including: design concepts, design target data, and evaluation tools, especially those using basic probability theory and simple queuing theory.
ShowKey Features
- Advanced concepts, such as wave and optimum pipelining, branch tables and prediction, superscalar designs, interconnection networks, and disk cache buffers.
- Design target data--instruction set data, branch data, cache data.
- Evaluation tools, queueing models for basic processor-memory, vector memory, interleaved caches, static and dynamic interconnections, and disk arrays.
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ShowTable of Contents
Preface
Acknowledgements
1. Architecture and Machines
2. Time, Area, and Instruction Sets
3. Data: How Programs Behave
4. Pipelined Processor Design
5. Cache Memory
6. Memory System Design
7. Concurrent Processors
8. Shared Memory Multiprocessors
9. I/O and the Storage Hierarchy
10. Processor Studies
Appendices:
A. DTMR Cache Miss Rates
B. SPECmark vs.. DTMR Cache Performance
C. Modeling System Effects in Caches
D. New DRAM Technologies
E. M/G/1 Queues
F. Some Details on Bus-Based Protocols
Bibliography
Index
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ShowAbout the Author(s)
Michael J. Flynn-Stanford University, Stanford, California
Michael J. Flynn, Stanford University, Professor Emeritus
Professor of Electrical Engineering.
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ShowAppropriate Courses
Intended for practicing computer designers and for students who have computer design as a professional objective.
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